In general, as shown in Drawing 7, a memory card 1 consists of one or two semiconductor memory areas (e.g., SRAM) 2 into which information can be written or from which information can be read, and a logic circuit 3 equipped with buffers 3a, 3b, and 3c. These buffers transfer to the semiconductor memory area 2, the address signal A coming from an external element such as a computer, the card enable signal CE, and the read/write signal RW. A data signal D is transferred directly either into or out of the semiconductor memory area 2 without going through a buffer. When the address signal A comes in from outside and is supplied to the semiconductor memory 2 via buffer 3a, the card enable signal CE, which is active within the same machine cycle, comes in and is supplied to the semiconductor memory area 2 via buffer 3b, activating the semiconductor memory area 2. Then, depending on the status of the read/write signal RW, the data signal D is either written into or read from the semiconductor memory area 2. However, this memory card configuration suffers from the problems described below.
In this configuration, the card enable signal CE from outside is applied without any change to the semiconductor memory area 2 via buffer 3b. However, when the semiconductor memory area 2 is accessed according to ascending or descending addresses, that is, when the address signal A changes randomly, the card enable signal CE supplied from an external computer also alternates between an active and inactive state every time the address signal A changes (for each continuous machine cycle). Consequently, the semiconductor memory area 2 alternates between the active and inactive states at a very high speed. When these transient changes in the semiconductor memory area 2 are severe, the pass-through current, etc. that flows through the internal circuit (consisting of a CMOS inverter, etc.) of the semiconductor memory area 2, becomes extremely high, thus inevitably resulting in a high level of current consumption by the semiconductor memory area 2. A more detailed explanation of this phenomenon follows. In general, when the enable signal CE of the semiconductor memory goes active, the level of current consumption increases over that experienced when the chip enable signal CE is inactive, due to the current that flows in the sense amplifier, etc. of the data line. Furthermore, the repeated alternation of the enable signal CE between the active and inactive states actually increases the pass-through current inside the CMOS circuit and the charging/discharging current, due to the wire capacitance. Whether the increase in current caused by the active state of the enable signal CE is larger or smaller than the increase caused by the repeated alternation of the enable signal CE between the active and inactive states, mainly depends on the circuit configuration of individual semiconductor memory components.
When an individual address signal is connected to both the enable signal CE, and an AND gate inside a semiconductor memory component and the address signal is incremented by +1 while the enable signal CE remains active, a minimum number of address signals are changed. On the other hand, when the enable signal CE repeatedly alternates between the active and inactive states, many address signals are internally changed at the point when the enable signal CE changes from the inactive state to the active state. This phenomenon increases the pass-through current inside the CMOS circuit and the charging/discharging current, due to the wire capacitance. In internally synchronized memory components that possess a so-called address transition detector (ATD) inside the semiconductor memory, repeated alternation of the enable signal CE between the active and inactive states changes many addresses, and also increases the pass-through current in the ATD and the charging/discharging current, due to the wire capacitance. Therefore, repeated alternation of the enable signal CE between the active and inactive states increases the pass-through current, etc. to an extremely high level inside the semiconductor memory, thus increasing current consumption. This level of power consumption shortens the battery life in battery-driven memory cards, and is thus unfit for actual applications in some cases.
Taking the above-mentioned problems into consideration, the objective of this invention is to provide a semiconductor memory device that reduces the current consumption of the semiconductor memory area, when the address signal changes randomly, by reducing the frequency at which the enable signal, which is applied to the semiconductor memory area, alternates between high and low.